Modeling and simulation of STacked Gate Oxide (STGO) architecture in Silicon-On-Nothing (SON) MOSFET

The paper presents the results of a systematic analytical characterization, supplemented by 2D device simulation, applied to novel device architecture: STacked Gate Oxide Silicon-On-Nothing (STGO SON) MOSFET with effective channel length down to 80 nm. A new approach to explain the pertinent device physics is presented, which can facilitate device design and technology selection for enhanced performance. Numerical device simulation data, obtained using 2D Device simulator: ATLAS, for (a) scale length, (b) potential and electric field distribution and (c) threshold voltage were compared to validate the analytical formulation. Comparison with simulated results reveals excellent quantitative agreement.