Transient blocking characteristics of highly efficient junction isolations based on standard CMOS process

This paper investigates the performance of single and multiple junction isolation structures for smart power IC's with regards to transient carrier injection. Both, single and multiple isolation structures are produced using a standard CMOS process all using the same surface area. The devices are based on different active junction isolation principles and it is shown that combinations of these devices can significantly improve the blocking characteristics of the isolation without an increase in surface area. It is shown that the transient current rejection of the devices is markedly different from their dc blocking characteristics. Considerations for the design of efficient isolation structures are discussed.