Modeling of transient drain current overshoot in polycrystalline silicon thin-film transistors

Turn-on transient drain current in polycrystalline silicon thin-film transistors is investigated. We consider two mechanisms responsible for causing the overshoot current, i.e., the carrier trap effect (CTE) and the self-heating effect (SHE). Under low drain bias, current decay is described by the power-law relaxation indicating CTE. Meanwhile, when input power is increased, the overshoot component associated with SHE is superposed, for which the stretched exponential function provides a better representation. We discuss the mechanisms behind the observed characteristics, and propose a semi-empirical equivalent circuit model to reproduce the transient behavior especially focusing on CTE.