Effect of internal stresses on thermo-mechanical stability of interconnect structures in microelectronic devices

Interconnect structures in microelectronic devices can deform via unusual, scale-sensitive phenomena due to thermo-mechanical loads sustained during processing, or during service as part of a microelectronic package. Examples include creep/plasticity of Cu interconnect lines embedded in a dielectric layer at the back-end of Si chip, and diffusionally accommodated sliding at Cu–dielectric interfaces. These effects may result in in-plane (IP) changes in Cu line dimensions, cause strain incompatibilities between Cu and LKD in the out-of-plane (OOP) direction, and cause Cu lines to migrate or crawl under far-field shear stresses imposed by the package. In this paper, a shear-lag based model is utilized to simulate IP and OOP deformation in a Cu–LKD interconnect structure on a Si substrate under thermal cycling conditions associated with processing. A separate model, which simulates IP deformation of Cu interconnects embedded in LKD under thermo-mechanical cycling conditions imposed when the chip is attached to a package, is also presented. The models, which incorporate a constitutive interfacial sliding law developed previously, help rationalize experimental atomic force microscopy (AFM) observations of inelastic strain accrual in Cu lines, and the development of dimensional incompatibility between adjoining components in devices, during thermal cycling.