Cohesive failure analysis of an array of IC chips bonded to a stretched substrate

• Presenting a mechanical model to analyze chip-array on stretched substrate.
• Supplying a precise solution to get ERR and adhesive stresses in adherend.
• Obtaining geometrical and material effects on the chip-on-substrate structure.
• Showing the interaction between the chips on the interfacial peeling.

The paper presents a mechanical model for predicting the cohesive failure of a periodic array of integrated circuit (IC) chips adhesively bonded to a stretched substrate. A unit cell of the layered structure consisting of the IC chips, adhesive layer, and substrate is modeled as an assembly of two elastic Timoshenko beams, representing the chip and substrate, connected by an elastic interface, representing the adhesive. Accordingly, the stresses and energy release rate (ERR) in the adhesive layer – responsible for the premature cracking of the adhesive and debonding of the IC chips – are identified with the corresponding quantities computed for the elastic interface. Expressions for the adhesive stresses and ERR are given in terms of geometrical dimensions and material properties, combined with integration constants obtained numerically via the multi-segment analysis method. For comparison, the stresses in the adhesive are also computed based on a finite element model, and the ERR is evaluated using the virtual crack-closure technique (VCCT). The analytical predictions and numerical results match fairly well, considering the effects of key factors, such as the distance between adjacent chips, the chip size, the material properties of adhesive and substrate. The interaction between the chips is shown to have relevant effects on the adhesive stresses. In particular, only the mode II contributes to the ERR which increases with the ratio of the chip size to the distance between the chips and with the compliance of the adhesive and substrate layers.