Revisiting 3DIC benefit with multiple tiers

3DICs with multiple tiers are expected to achieve large benefits (e.g., in terms of power, area) as compared to conventional planar designs. However, few if any previous works study upper bounds on power and area benefits from 3DIC integration with multiple tiers. In this work, we use the concept of implementation with infinite dimension to estimate upper bounds on power and area benefits achievable by 3DICs versus 2DICs. We observe that the maximum power benefit even with infinite dimension can be only 18% versus 2DIC for particular designs. Such benefits reduce further under assumptions of inter-tier variation. We confirm our observation by performing 3D benefit estimation across various technologies. Our study also indicates that it is typically difficult for pure logic-logic 3D integration to achieve a simultaneous (10%, 10%, 10%) improvement in (performance, power, area/cost) compared to the conventional 2D implementation. In addition, we study power of designs across various dimensions (e.g., pseudo-1D, 2D, 3D with two, three and four tiers).1 We observe that design power sensitivity to implementation with different dimensions correlates well with placement-based Rent parameter of the netlist. Therefore, placement-based Rent parameter can possibly be a simple indicator of 3D power benefit. Our study also shows that netlist synthesis and optimization should be aware of the target implementation dimension (e.g., 2D versus 3D). Finally, we use a simple example to show that there remain potential large 3DIC benefits versus 2DIC for (block-based) SoC designs.