On supporting rapid prototyping of embedded systems with reconfigurable architectures

- We present a modern virtual prototyping platform and identify some of the most time-consuming steps in development.
- We define and extract necessary task information through profiling, high-level synthesis and task execution on an FPGA.
- We model task mapping as an optimisation problem and solve it with genetic algorithms.
- We optimise the hardware-assigned tasks assigned to hardware by performing further DSE with the help of FPGA.

Reducing time-to-market while improving product quality is a big challenge. This paper proposes a software-supported framework for rapid prototyping that offers a concurrent fast hardware/software system-level design. The introduced framework enables the constant evaluation and verification of the prototype under development, while it provides automatic functionality mapping to hardware via High-Level Synthesis techniques. We evaluate our framework and its software instantiation with a computer vision algorithm. Based on our experimentation, we show that our approach reduces the development time by almost 64×, it prunes the hardware design space by 34×, while maintaining designs that trade-off high Quality-of-Report on the Pareto frontier.