On advance towards sub-sampling technique in phase locked loops - A review

This paper presents a symmetric review of academic and accomplished research endeavors in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has been given to understand the yearn for development of Sub-Sampling PLLs. Techniques that have emerged over the recent few years in context of better FOM, Jitter and Phase Noise reduction while maintaining extraordinary circuit performance in Sub-Sampling PLLs with CMOS/VLSI technology, have been captured in this paper. Consecutively, the main inspiration of this study is to present an overview of the PLL fundamentals, furtherance from analog to Digital PLL and various noises encountered in the different PLL components, important for the reader to have a better understanding about the design and analysis of Sub-Sampling PLLs.