A constrained optimization approach for accurate and area efficient bandgap reference design

In this paper, a constrained optimization approach for the design of bandgap reference (BGR) circuits that meet a given voltage inaccuracy specification while minimizing area is presented. Device matching properties and error propagation analysis are carried out such that the desired performance can be achieved by the optimization algorithm. The BGR occupies 0.097 mm2 in a 0.35μm CMOS process. Experimental results verified the effectiveness of the optimization algorithm by producing a voltage reference of 1.220 V, with a relative inaccuracy (3σ/μ) of 0.65% at 27°C and TC=13.7ppm/°C in the range of −10°C to 125°C, for all 40 fabricated samples, without trimming. Also shown in the paper and verified experimentally, a 3-fold reduction in inaccuracy, to 0.20% at 27°C, can further be obtained, if needed, by a simple one-temperature four-bit trimming.