Low Leakage Single Bitline 9Â T (SB9T) Static Random Access Memory

This paper presents a low leakage, half-select free SB9T SRAM cell with good static and dynamic read/write performance along with smaller area. The proposed cell offers high Read SNM and low leakage power among the cells considered in this work while causing an area overhead of only 37% of that of 6T cell. Simulation results show that the proposed cell offers 4.2x higher RSNM, 33% lower mean leakage power as compared to 6T SRAM. The proposed cell also offers more than 10x higher Ion/Ioff ratio that holds potential to compensate for the area overhead by having more number of cells connected to the same bitline. The proposed cell has longer write delay because of the single bitline structure; however, it offers lower read delay and smaller read/write power to that of the 6T cell. Monte Carlo simulations using HSPICE at 16nm technology were performed by incorporating local and global variations and it is observed that the proposed cell offers high robustness against process variations. Therefore, the proposed cell could be a good choice for applications that demand high stability, low power, low area and moderate speed.