Efficient utilization of imprecise computational blocks for hardware implementation of imprecision tolerant applications

Recently, it has been reported that exploiting imprecise arithmetic building blocks such as adders and multipliers significantly improves digital implementation costs as well as performance of an important category of systems named as Imprecision Tolerant (IT) applications. We have categorized this new type of functional units as Bio-inspired Imprecise Computational (BIC) blocks. To efficiently exploit BICs in an IT application, however, the traditional hardware design flow should also be customized based on unique features of this new type of computing blocks. The most significant modification on traditional design flow to maximize the cost-performance of BIC implementations is to verify that the application is capable of tolerating those types of errors which are inherently introduced by the selected BIC based on its internal structure. We call this “error-behavior compatibility matching” between the system and the selected BIC building blocks. In this paper, we introduce and explain a customized hardware design flow for BICs with the main focus on error-behavior compatibility matching process as the main difference between traditional and BIC design flows. Two different error-behavior compatibility matching strategies are also introduced and their applicability is verified by applying them to exploit BICs for hardware implementation of some significant case studies including a general multiply-accumulate (MAC) block as the basic building block of many signal processing applications as well as an Artificial Neural Network (ANN) as a critical instance of MAC-based IT applications.