SEU reduction effectiveness of common centroid layout in differential latch at 130-nm CMOS technology

In this paper, we apply the common centroid layout technique in a differential latch structure (i.e., Quatro) and evaluate its effectiveness in reducing single event upset vulnerability. SPICE simulations demonstrate that higher charge sharing efficiency between the differential pair of sensitive devices results in higher critical charge of the latch. Both regular and common centroid layouts show the same heavy ion upset Linear Energy Transfer (LET) threshold because this is determined by the worst case critical charge (i.e., there is no charge sharing). Additionally, the magnitude decrease in the cross section of common centroid layout than that of the regular layout is not significant in 130-nm CMOS bulk technology because cross section covers the highest charge sharing efficiency and the lowest charge sharing efficiency from statistical point of view.