Determination of safe reliability region over temperature and current density for through wafer vias

- Slot and circular GaAs vias were subjected to stress over temperature and current.
- Failure times were fitted to Black's equation.
- The FIT rate of both vias were shown on contour maps of constant FIT rate revealing where the via can be operated reliably.
- Both circular and slot vias met the goal of 100 FITs in 10y at T=125C and J = 0.25 x106 A/cm2.

Circular and slot backside vias are stressed over current and temperature and the resulting failure times are fitted to Black's equation. Contour plots of the FIT rate are generated and the reliability of circular and slot vias are compared. It is demonstrated that in most cases the FIT rate of the circular via is statistically significantly lower than that of the slot via. However, both types are easily able to meet a goal of 100 FITs in 10 years at T = 125 °C and J = 0.25 × 106 A/cm2. The contour map of the FIT rate defines the region where the via can operate reliably. By use of the 95% upper confidence bound, the region of safe operation is reduced in size, adding a layer of margin to the prediction of via reliability. The approach described here provides a “reliability map” for designers allowing trade-offs between temperature current to be made when designing for high reliability.