Analysis of aging effects - From transistor to system level

This work presents methods to investigate the influence of age-dependent degradation as well as process-variability on different levels. An operating-point dependent sizing methodology based on the gm/ID-method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced.