Analysis and design of notch filter-based PLLs for grid-connected applications

Using multiple notch filters (NFs) inside the control loop of a standard PLL is a basic strategy to improve its filtering capability. Often, adaptive NFs (ANFs) are employed for this purpose as they can block the disturbance components even under off-nominal grid frequencies. This advantage is at the cost of a rather considerable increase in the PLL implementation complexity and computational effort, particularly when ANFs have their own frequency estimation mechanism. The non-adaptive NFs (NNFs), contrary to ANFs, are easy to implement. They, however, have received a little attention in PLL applications. Therefore, their performance characteristics are rather unclear. To gain insight about the advantages and disadvantages of NNF-based PLLs (NNF-PLLs), analysis and design of these PLLs is conducted in this paper. This procedure includes: (1) selecting the appropriate number of NNFs inside the PLL control loop, (2) approximating dynamics of cascaded NNFs with a simple first-order low-pass filter, which simplifies the tuning procedure, (3) applying the symmetrical optimum method for selecting the control parameters of the NNF-PLL, and (4) performing extensive experimental results. The obtained results indicate that NNFs can sufficiently mitigate disturbances caused by the presence of harmonics in the PLL input while maintaining a fast dynamic response for the PLL. To be more exact, the NNF-PLL can provide a settling time around 2 cycle of the nominal frequency during phase and frequency jumps while having a peak-to-peak phase error less than 0.2° under a heavily distorted grid condition (THD = 15%). It, however, may not be able to effectively reject the double-frequency disturbance component caused by the grid voltage unbalance. To deal with this problem, a hybrid combination of adaptive/nonadaptive NFs is suggested in this paper. The experimental results show that the resultant PLL, which is called the HNF-PLL, completely removes the grid voltage unbalance, effectively suppresses harmonics, and offers a fast dynamic response (a settling time around 1.5 cycle of the nominal frequency). The ease of implementation is kept in the HNF-PLL as only one of the NFs is adaptive and this NF does not require a separate frequency estimation mechanism.