کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
5010324 | 1462205 | 2017 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100Â K
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100Â K Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100Â K](/preview/png/5010324.png)
چکیده انگلیسی
This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 128, February 2017, Pages 60-66
Journal: Solid-State Electronics - Volume 128, February 2017, Pages 60-66
نویسندگان
Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello,