Simulation study of a novel 3D SPAD pixel in an advanced FD-SOI technology

In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI) CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution is expected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixel and the detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters and dedicated post-processing analysis are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device but also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability, the dark count rate and the photon detection probability. A comparison between the efficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flight applications.