Statistical lifetime reliability optimization considering joint effect of process variation and aging

Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability, identifies a set of worst duty cycles on the inputs of statistically critical gates to estimate the worst delay degradations on these gates. Based on the delay degradation information, statistical gate sizing is performed which enables the manufactured chip to satisfy lifetime reliability constraint in term of low area overhead.