Crosstalk-aware multi-bit flip-flop generation for power optimization

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger number of bits as possible to gain more clock power saving. However, an MBFF with larger number of bits may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. This paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different numbers of bits. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization.