A novel autozeroing technique for flash Analog-to-Digital converters

• A novel autozeroing technique for flash ADCs is presented.
• Several drawbacks of traditional interpolation-based techniques are solved.
• A 6-bit 1 GS/s 0.13 µm flash ADC with capacitive interpolation has been designed.

This paper presents a new autozeroing technique that combines very high speed operation, low power consumption and low input switching interferences. This technique has been applied to the design and implementation of a 6-bit 0.13 μm CMOS flash Analog-to-Digital converter for Ultra-Wide Band applications. Simulation results show 5.76-bit at 1 GS/s with a power consumption of only 182 mW, validated with experimental measurements carried out with 3-bit circuit tiles of the 6-bit flash A/D converter.