Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs

With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Therefore, it is necessary to consider Power/Ground network design with thermal effects in 3D designs. Though Power/Ground (P/G) TSV can help to relieve the IR drop violation by vertically connecting on-chip P/G networks on different layers, most previous work restricts the uniform P/G grids so that the potential of P/G TSV planning has not been fully explored. In this paper, we present an efficient thermal-aware P/G TSV planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. Non-uniform P/G grid topology is explored to optimize the P/G network by allowing short wires to connect the P/G TSVs to P/G grids. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3% and reduce the number of violated nodes by 82.4%.

► Thermal aware IR drop analysis is proposed in 3D IC to support the P/G TSV planning.
► A sensitivity model of P/G TSV insertion is proposed to guide the P/G TSV planning.
► Short wires are adopted to connect the P/G TSVs to P/G grids in non-uniform grids.