کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
540985 | 1450236 | 2015 | 10 صفحه PDF | دانلود رایگان |
• An efficient method for setup / hold time constraints using Finite-Point approach.
• Critical data points abstracted from non-linear curve of timing characteristics.
• Significant reduction in computation cost and data volume achieved.
• Accuracy comparable to SPICE simulation data.
• Same approach can be extended for all sequential cells for all technology nodes.
Timing characterization of sequential elements, such as latches and flip-flops, is one of the critical steps for timing closure in the pipelined design. Traditional characterization of setup and hold time constraints is computationally intensive, due to the demand on high accuracy in monitoring the operation failure. To improve the efficiency, this work proposes a finite-point based method for the characterization of setup and hold time constraints. The finite-point method identifies several critical data points in the non-linear curve of timing characteristics, and abstracts the essential setup/hold information from them. Moreover, compact models are derived for each point, further reducing the computation cost. The proposed method is general for all sequential elements in the standard cell library. It is comprehensively validated using benchmark circuits at 45 nm node. Experimental results demonstrate approximately 25× reduction in characterization time, with the prediction error in setup and hold time within 9% of FO4 nominal delay, as compared to that of SPICE simulation results.
Journal: Integration, the VLSI Journal - Volume 49, March 2015, Pages 104–113