Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design

We propose a physical design methodology for synthesis using soft hierarchy, interior pin placement, pre-placing critical logic, and routing techniques on a very timing- and area-challenged unit, the L2 cache, with ~20 million synthesizable transistors. In any past and present standard design at IBM, this test case would stretch all front- and back-end design tools by two to three times due to data volume, congestion and timing criticality, which opens a new avenue to explore for Large Block Synthesis flow. The results confirm the ability to deliver a design in the shortest possible schedule at ~50% of Physical Design cost while still maintaining best-of-breed quality.