On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

• High-throughput and area-efficient SHA-256/512 and SHA-1/256/512 multi-mode architectures.
• Systematic design flow for developing multi-hash-mode architectures.
• Comparisons with multi-mode architectures produced by commercial synthesis tools.
• Comparisons of the proposed architectures with similar ones found in the literature.

In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.