A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

State of the art multi-objective synthesis flows use to degrade some parameters of the circuit while trying to optimize the target one. This paper addresses the power reduction problem in heterogeneous datapaths, while keeping a similar area and execution time with respect to the baseline case. Our specific approach first diminishes the area via fragmentation techniques and afterwards it gives it back with the introduction of Low Power Functional Units (LP-FUs) that occupy more area than their corresponding non-low power counterparts. Furthermore, a fragmentation algorithm more suitable for power reduction is proposed. Results show that it is possible to diminish power by 27% on average (49% in the best case).

► Low Power Functional Units (LP-FUs) utilize more area to diminish the switching activity.
► We use these LP-FUs without penalizing the other parameters.
► First area is reduced and afterwards it is given back to use LP-FUs.