Keywords: سنتز سطح بالا; Heterogeneous SoCs; Hardware accelerators; High-level synthesis; Templates; Acceleration; Simulation;
مقالات ISI سنتز سطح بالا (ترجمه نشده)
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Keywords: سنتز سطح بالا; Discrete-event modeling; High-level synthesis; Industrial Internet of Things (IIoT); Smart sensor network;
Keywords: سنتز سطح بالا; High-level synthesis; Designer productivity; Quality of results; Reliability; Security; Verification; Validation; Time to market; Modeling; Performance; Low power; Area cost; Polyhedral optimization; Parallel languages; Interconnect optimization; Variatio
Keywords: سنتز سطح بالا; reconfigurable architecture; pipeline computations; high-level synthesis; parallelizing compiler; high-level internal representation; FPGA; HDL;
Keywords: سنتز سطح بالا; Multi-spectral image processing; Light–Tissue Interaction; Genetic Algorithm; Embedded System; FPGA; High-Level Synthesis
Keywords: سنتز سطح بالا; High-Level Synthesis; Design Space Exploration; FPGA; Hardware accelerators; Resource constraints
Design space exploration of multi-core RTL via high level synthesis from OpenCL models
Keywords: سنتز سطح بالا; Design space exploration; Data center; FPGA; GPU; OpenCL; High-level synthesis; Low-power low-energy computations; Parallel computing;
An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem
Keywords: سنتز سطح بالا; Genetic algorithms; FPGA; Array processor; High-level synthesis;
Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation
Keywords: سنتز سطح بالا; High-level synthesis; Low power design; Power management; System-level specification; Verification;
Efficiency analysis methodology of FPGAs based on lost frequencies, area and cycles
Keywords: سنتز سطح بالا; FPGA; Lost cycle analysis; Performance efficiency; High-Performance Computing; High-Level Synthesis; Vivado HLS;
A robust multispectral palmprint matching algorithm and its evaluation for FPGA applications
Keywords: سنتز سطح بالا; Multispectral biometric authentication; Real-time image processing; Partial least square regression; Embedded system; High-level synthesis;
Fast and efficient power estimation model for FPGA based designs
Keywords: سنتز سطح بالا; Design space exploration; High-level synthesis; Power estimation; Field programmable gate array (FPGA); Low level virtual machine intermediate representation (LLVM IR); Artificial neural network (ANN);
Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs
Keywords: سنتز سطح بالا; OpenCL; LDPC; FPGA; High-level synthesis; Altera-Offline Compiler; Low-Density Parity Check; Parallel algorithms;
Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis
Keywords: سنتز سطح بالا; Fault tolerance; Multi-unit transient fault; Multi-cycle transient fault; High-level synthesis; Low cost design; Loop unrolling; CDFG;
A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)
Keywords: سنتز سطح بالا; All-digital phase locked loop; High-level synthesis; Phase domain model; Phase noise estimation;
LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow
Keywords: سنتز سطح بالا; High-level synthesis; RTL; Design space exploration; Common power format; Low power designs; Design automation; EDA methodologies;
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors
Keywords: سنتز سطح بالا; Multiple transient faults; Multi-cycle transient fault; High-level synthesis; Physical design; Resiliency
Improving circuit performance with multispeculative additive trees in high-level synthesis
Keywords: سنتز سطح بالا; Variable-latency functional units; Speculation; Additive operation trees; High-level synthesis;
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Keywords: سنتز سطح بالا; 3D IC design; Through-silicon-vias; High-level synthesis; Interconnect optimization; Resource sharing
A metaprogrammed C++ framework for hardware/software component integration and communication
Keywords: سنتز سطح بالا; System-on-Chip; System-level design; High-level synthesis; HW/SW co-design; HW/SW communication
Compiling for power with ScalaPipe
Keywords: سنتز سطح بالا; FPGA; Embedded systems; Energy; High-level synthesis
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Keywords: سنتز سطح بالا; Low power; Area; High-Level Synthesis
Design space exploration for high-level synthesis of multi-threaded applications
Keywords: سنتز سطح بالا; Electronic system-level design; OpenMP; Design space exploration; High-level synthesis; FPGA
Design of multi-mode application-specific cores based on high-level synthesis
Keywords: سنتز سطح بالا; CAD; High-level synthesis; VLSI design
FPGA-specific synthesis of loop-nests with pipelined computational cores
Keywords: سنتز سطح بالا; High-level synthesis; FPGA; Data-reuse; Polyhedral compilation; Pipelined arithmetic operators; Floating-point; Parallelization; Kernel accuracy
Finding the best compromise in compiling compound loops to Verilog
Keywords: سنتز سطح بالا; High-level synthesis; FPGA; Compilation;
Performance-driven scheduling of behavioural specifications
Keywords: سنتز سطح بالا; Scheduling; High-level synthesis; Design automation; Allocation; Binding
Improving evolutionary exploration to area-time optimization of FPGA designs
Keywords: سنتز سطح بالا; High-level synthesis; FPGA; Evolutionary algorithms; Multi-objective optimization; Fitness inheritance
Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times
Keywords: سنتز سطح بالا; Cyclic scheduling; Integer linear programming; High-level synthesis; Changeover times; FPGA
A Novel Register Allocation Algorithm for Testability
Keywords: سنتز سطح بالا; high-level synthesis; register allocation; testability; compatibility graph; clique partition algorithm;
FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan
Keywords: سنتز سطح بالا; high-level synthesis; floorplan; interconnect delay; re-synthesis; reschedule; reallocation;
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Keywords: سنتز سطح بالا; High-level synthesis; Low power; Multiple supply voltages; Partitioning; Scheduling
A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis
Keywords: سنتز سطح بالا; High-level synthesis; Switching activity; Low power; Simultaneous scheduling and binding
Verification method of dataflow algorithms in high-level synthesis
Keywords: سنتز سطح بالا; Formal verification; High-level synthesis; Petri Net; Dataflow graph;
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
Keywords: سنتز سطح بالا; Optimization; Data-flow; Genetic algorithm; High-level synthesis; Field-programmable gate array;
System petri net specification
Keywords: سنتز سطح بالا; digital controllers; high-level synthesis; system specification; XML;
A PN-based approach to the high-level synthesis of digital systems
Keywords: سنتز سطح بالا; High-level synthesis; Object-oriented model; Petri nets; Requirements analysis; Rapid protyping
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
Keywords: سنتز سطح بالا; Discrete wavelet transform; High-level synthesis; Intellectual property (IP) core; JPEG2000; Lifting scheme
Time-constrained scheduling of large pipelined datapaths
Keywords: سنتز سطح بالا; Scheduling; High-level synthesis; Allocation; Pipeline; Genetic algorithm; Constraint logic programming;