A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit

A high-speed low active and leakage power SRAM memory is developed for mobile processors. The sleep controller for cell arrays and power cut-off for peripheral circuits are used for low leakage current in standby mode, while the leakage power in active mode is decreased by about 4% using the distributed decoders with virtual ground control. In addition, the read and write divided timing control is adopted to reduce the write current by about 25%. The delay variation due to process variation is mitigated by the programmable timing control with an embedded built-in self-test (BIST) and the compact timing control is achieved, resulting in lower active energy. The designed 16 kbit memory is fabricated in 65 nm LP process. It operates up to a speed of 1.24 GHz while consuming the leakage power of 1.16 μW in the standby mode and the active energy of 11.1 pJ/access for a word length of 32 bit.