Timing yield analysis considering process-induced temperature and supply voltage variations

Process variations cause fluctuations in the threshold voltage of integrated circuits (ICs). The variations, in turn, lead to uncertainties in the leakage current, drawn off the power grid that the underlying circuit is connected to. Because of the interdependency between the leakage power and temperature, process variations impose statistical behavior on the nodes’ supply voltage and also on the temperature. In addition, the resistivity of the interconnects increases with temperature. Consequently, the imposed variations significantly impact the performance of devices and interconnects.This paper presents a statistical analysis of the timing yield by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This helps to accurately estimate the timing yield and check the robustness of the circuits early in the design process and avoid over-design. Monte-Carlo simulations on ISCAS89 benchmarks verify the accuracy of the proposed methodology.