Comparison of transient and static test methods for chip-to-sink thermal interface characterization

Accurate thermal interface characterization is essential for high flux microelectronic package design. However, it is increasingly difficult as interfacial bond lines are thinned and thermal interface materials (TIM) evolve to more complex formulations with better performance. This paper compares a static versus transient characterization method targeted at the chip-to-package interface in a test fixture that closely resembles a packaged chip. The static method requires measurements over multiple bond line thicknesses while the transient method yields additional information about the package at the cost of greater numerical complexity, hardware requirements, sensitivity to noise and experimental uncertainty. Both are compared with existing techniques. We conclude that the static method is more generally-applicable while transient is well-suited to rapid characterization of the interface when the rest of the package is well-defined. While both methods are sensitive to the accuracy and resolution of temperature and bondline thickness measurements, the transient technique is additionally sensitive to the relative contribution of the TIM in the full junction-to-ambient thermal path. These points are illustrated through experimental results and compact numerical modeling.