UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

• UA2TPG supports on-line testing of the configuration memory of SRAM-based FPGAs.
• Off-line detection of untestable SEUs reduces ATPG search space.
• Only the configuration bits used by the specific application are considered.
• Model checking is used to formally prove untestability and generate test patterns.
• Results show test pattern generation with 100% coverage of testable SEU events.

This paper presents UA2TPG, a static analysis tool for the untestability proof and automatic test pattern generation for SEUs in the configuration memory of SRAM-based FPGA systems. The tool is based on the model-checking verification technique. An accurate fault model for both logic components and routing structures is adopted. Experimental results show that many circuits have a significant number of untestable faults, and their detection enables more efficient test pattern generation and on-line testing. The tool is mainly intended to support on-line testing of critical components in FPGA fault-tolerant systems.