A novel spatially configurable differential interface for an electronic system prototyping platform

• A complete experimental validation of a spatially configurable differential interface.
• A spatially configurable differential interface that can be adapted and used in FPGAs.
• The interface can be enhanced to accommodate other differential signaling standards.
• Prototype test-chip was tested and conclusive experimental results are reported.

This paper presents complete and detailed circuit design, and the first experimental validation of a previously proposed spatially configurable differential interface that was designed to support current mode logic (CML) on a reconfigurable electronic system prototyping platform. The physical and electrical constraints of CML interfaces are described, and an architecture is proposed for transmitting differential signals between two different integrated circuits (ICs) deposited on the prototyping platform surface. The proposed implementation has been validated in a test-chip using a mature 0.18μm CMOS technology. Measurements on the test-chip show that the spatially configurable differential interface can operate at a speed of up to 2.5 Gbps.