کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
542885 | 871592 | 2008 | 15 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Low-power multi-core ATPG to target concurrency
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 41, Issue 4, July 2008, Pages 459–473
Journal: Integration, the VLSI Journal - Volume 41, Issue 4, July 2008, Pages 459–473
نویسندگان
Arkan Abdulrahman, Spyros Tragoudas,