High speed true random number generator based on open loop structures in FPGAs

Most hardware “True” Random Number Generators (trng) take advantage of the thermal agitation around a flip-flop metastable state. In Field Programmable Gate Arrays (fpga), the classical trng structure uses at least two oscillators, build either from pll or ring oscillators. This creates good trng albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This speed requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution protocols. The proposed architecture is very simple and generic as it is based on an open loop structure with no specific component such as pll.