Hardware accelerated FPGA placement

A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic blocks, more efficient and scalable FPGA placement algorithms are needed. This paper investigates the feasibility of using hardware acceleration, in the form of FPGAs, to improve the performance of placement algorithms. An iterative algorithm is presented which exploits the fine-grain parallelism in routing individual nets. Overall, our results show that speedups of 3–4 times can be obtained, without sacrificing solution quality.