Fault-tolerant TMR and DMR circuits with latchup protection switches

• The ASIC design flow is modified to protect circuits from the single event effects.
• The protection switch is verified by measurements in radiation environment.
• TMR and DMR shift-registers with latchup protection are designed and tested.
• DMR with protection switch outperforms TMR in terms of failure-free probability.
• The fault-tolerant DMR middleware switch processor is designed and implemented.

The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.