A low power low area capacitor array based Digital to Analog Converter architecture

This paper presents a capacitor based Digital to Analog Converter architecture, which gives comparable performance with the conventional architecture with approximately half the total capacitance. The proposed architecture reduces the area and power dissipation in comparison with the conventional scheme. Further to these advantages, the proposed DAC architecture does not demand an additional reference voltage or an additional switching circuit. Closed form formulas to estimate the standard deviation of INL, DNL and the power consumption are derived. A comparison is also made between the standard architectures and the proposed architecture for the same unit capacitor, in addition to analyzing the capacitor parasitics and mismatches. These analytical comparisons are validated by simulating the proposed architecture and all the other conventional architectures for 10 bits with UMC 180 nm CMOS technology.