Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells

In this paper, two ultra-low power Single Walled Carbon Nanotube Field-Effect Transistor (SWCNFET) based SRAM cells are proposed to minimize static power dissipation due to leakage. The proposed first cell consists of six transistors (6T) with dual-gate n-type CNFETs whose back gates are negatively biased and the second cell employs stack forcing in the pull down n-type transistors of the cell, resulting in a symmetric eight transistor (8T) SRAM cell structure. The cells are designed with dual chirality and analyzed through simulation at two different temperatures (25°C and 110°C). A 6T CNFET based SRAM with dual chirality presented in reference literature is taken as reference for benchmarking the performance of the proposed cells. The proposed cells are effective in reducing the leakage power by more than 35% at 25°C and more than 60% at 110°C during standby mode of operation. Write leakage and average write power are also minimized at the expense of minimal increase (less than 5%) in write delay.

► Two ultra-low power CNFET SRAM cells are proposed with low static power leakage.
► Leakage reduction techniques include stack forcing and CNFET back gate reverse bias.
► The cells are designed with dual chirality and analyzed through simulation.
► The cells reduce standby leakage power by about 35% at 25°C and about 60% at 110°C.
► Write leakage and average write power are minimized with 5% increase in write delay.