On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD

A design evaluation is reported for multigate FETs (MuGFETs) by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool within the context of optimizing the device design and underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm MuGFET devices. Using our real process flow, various process simulation parameters from diffusion and activation models are first calibrated to the experimental data. Device simulations are then performed with varying fin doping, fin width, fin height, Ldd and halo implant tilt, and box thickness. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and short channel effects (SCEs) remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand drain-induced barrier lowering (DIBL), subthreshold slope (S) and off-current IOFF are quite sensitive to the variations in fin width (at fixed fin height). We found that the lower Ldd and halo implant tilt angle (20–30°) are beneficial in reducing the SCEs and off-current. Finally, a comparison of the simulation results with electrical measurement data is presented, which shows fairly good agreement.