Low-power multi-threshold MCML: Analysis, design, and variability

The increasing demand on low-power applications is adding pressure on circuit designers to come out with new circuit styles that can decrease power dissipation while making use of the performance improvement of the new CMOS technologies. Multi-threshold MOS current mode logic (MTMCML) appears to be a solution to this problem by making use of the high-performance of MOS current mode circuits while minimizing power dissipation with the help of multi-threshold CMOS technologies. In this work, analytical formulations, based on the BSIM3v3 model, are proposed for MTMCML performance measures with an error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.