Analysis design of area efficient segmentation digital to analog converter for ultra-low power successive approximation analog to digital converter

This article presents analysis design of area efficient segmentation analog to digital power successive approximation analog to digital converter. A 10-bit 10-kS/s successive approximation analog-to-digital converter (SAR ADC) is designed by using 0.18 µm CMOS technology. The SAR ADC has been designed by using the segmentation technique which employed two different digital to analog converter (DAC) architectures. The proposed DAC design shows significant reduction in terms of area and better linearity. The overall speed of the ADC has greatly reduced due to lower switching activity. The supply voltage used is 1.5 V. At 10-kS/s sampling rates, the total power consumption of the whole SAR ADC is equaled to 7 nW while for DAC alone is 2.7 nW.