Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In this paper a single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique (CC-LCFF) is proposed and proved to be suitable for use in low-power non-critical paths with Dual-VDD. CC-LCFF conditionally blocks the clock signal when the input data does not make any transition, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. Based on the SMIC 65 nm technology, the post-layout simulation results show that the proposed CC-LCFF shows an improvement of 69.41–72.40% in power consumption and 23.36–47.73% in power-delay product (PDP) as compared with its counterparts.