Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

• A universal testable parity preserving QCA logic (t-QCA) is designed.
• Results show the effectiveness of the design in terms of cost and testing overhead.
• Reliability issue is addressed with the success of 100% fault coverage.
• The t-QCA is able to detect permanent and transient faults concurrently.
• A simple augmented testing circuit using QCA primitives is designed.

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.