Design-for-testability techniques for CORDIC design

In this paper, we propose two C-testable design-for-testability (DFT) architectures for coordinate rotation digital computer (CORDIC) design. The first design is achieved by using scalable cells. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between hardware overhead (HO) and number of test patterns (NTP). Both HO and NTP change as n varies. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. Based on these scalable cells, the iterative logic array (ILA) will be still C-testable. For the first proposed design, the HO and NTP for n=2 are 5.37% and 74, respectively. The second one is achieved by the reorganized test sequences, where the HO and NTP are only 3.15% and 18, respectively. The first design can be connected into a non-homogenous ILA for saving lot of test pins and built-in self-test (BIST) area; in the second one, the special properties of the sequences reduce HO/NTP significantly.