کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
547838 | 872060 | 2009 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 40, Issue 6, June 2009, Pages 1007–1012
Journal: Microelectronics Journal - Volume 40, Issue 6, June 2009, Pages 1007–1012
نویسندگان
Yongseo Koo, Kwangyeob Lee, Kuidong Kim, Jongki Kwon,