Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

• The hot-carrier degradation of nanoscale n-FinFETs has been investigated under different bias stress conditions.
• The impact of HCs on the device parameters has been expressed in terms of the stress time, channel length, drain and gate biases.
• Based on our analytical compact model, HC aging model is proposed predicting the device degradation in all operating regimes.
• The impact of hot-carriers on a CMOS inverter is simulated using HSPICE.

The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.