3D thermal conduction in a nanoscale Tri-Gate MOSFET based on single-phase-lag model

With the introduction of the new silicon on insulator (SOI)-Tri-Gate MOSFET technologies, it is very necessary to simulate the thermal performance in these nano devices. We have to notice that heat conduction given by Fourier's law ceases to be valid in nanostructures, due to the finite heat propagation speed in nanoscale regime. In this paper, we propose a thermal model given by the 3D single-phase-lag (SPL) model to predict the phonon transport in a 3D MOSFET and a Tri-Gate SOI-MOSFET. Considering the phonon-wall collisions, the SPL model is coupled with a new 3D second-order temperature-jump boundary condition. Using the finite element method we found that our proposed model is able to predict the thermal performance of a 10 nm 3D MOSFET and a 10 nm Tri-Gate SOI-MOSFET. The results reveal that the increase of the wall number leads to a decrease of the temperature field in the Tri-Gate structures. The results prove also that the channel width has an important role in the increasing of the temperature.