Contention free delayed keeper for high density large signal sensing memory compiler

Compiler based embedded memory is essential for SoC design. A new Contention Free Delayed Keeper (CFDK) topology has been developed in a leading edge 14 nm System-on-Chip (SoC) technology to improve the read performance of register file (RF) memories which can be easily used for both high density (HD) and high performance (HP) RF memory compiler design. This technique never allows contention and this helps to improve Vmin (minimum operating voltage at which design is functional) significantly compared to a conventional keeper with low area overhead. It does not require fine tuning the keeper delay across the range of the local bit line (LBL) lengths that the compiler supports. It is shown that the proposed technique enhances the circuit evaluation speed by at least 68% while reducing power dissipation by 2.75% as compared to conventional domino logic. It also shows minimum 10% improvement in area with at par or better Vmin and performance over other delayed keeper techniques. The same technique can be broadly applied to any domino path design including ROM design.