کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
6942157 | 1450224 | 2018 | 13 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Metastability immune and area efficient error masking flip-flop for timing error resilient designs
ترجمه فارسی عنوان
خطای کارآیی سیستم ایمنی ماتریس و خطای کارکرد، ترسیم فلیپ فلاپ برای طرح های مقاوم در زمان خطا
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
چکیده انگلیسی
Reducing the worst case timing guard bands is one of the major concerns in high performance designs with limited power budget in the advanced nano-scale technology nodes. In this work, an error masking flip-flop is proposed to reduce the worst case timing guard bands by detecting and correcting timing violations. It consists of a pulse generator, an error detector and a multiplexer along with a conventional flip-flop. Exploiting an intermediate multiplexer between master and slave latch of a conventional flip-flop, the erroneous output state of the flip-flop due to timing violations is corrected by providing direct data to slave latch. The proposed flip-flop occupies 16% less area compared to error masking flip-flops available in literature. A core level clock gating is employed for error recovery which shifts the rising edge of the clock by one period in case of a timing violation. ISCAS'89 benchmark circuits, a 32-bit pipelined adder and a 16-bit pipelined multiplier are implemented in 130Â nm technology, which use error masking flip-flop for dynamic voltage and frequency scaling (DVFS). It is shown that using error masking flip-flops with DVFS can either reduce power consumption up to 20% or improve the performance up to 32% in typical operating conditions compared to worst case design.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration - Volume 61, March 2018, Pages 101-113
Journal: Integration - Volume 61, March 2018, Pages 101-113
نویسندگان
Govinda Sannena, Bishnu Prasad Das,