A new write assist technique for SRAM design in 65Â nm CMOS technology

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T-SRAM cell with transmission-gate access devices. The proposed design gives 2.7×, 2.1× faster write time, 82% and 18% improvement in write margin compared with the standard 8T-SRAM cell with and without write assist, respectively. All simulations have been done in TSMC 65 nm CMOS technology. The proposed write assist technique enables 10T-SRAM cell to operate with 24% lower supply voltage compared with standard 8T-SRAM cell with negative bitline write assist. Due to the improved supply voltage scalability a 33% leakage power reduction is achieved.