Statistical estimation of delay in nano-scale CMOS circuits using Burr Distribution

the process of modern integrated circuit (IC) design has been challenged by many factors. One of the most important challenges is the variation of device and circuit parameters during the manufacturing process. In this paper, the effects of manufacturing process variations on the gate delay have been modeled and an accurate yet low-cost simulation method for estimation of the circuit performance has been proposed. This additive method takes advantage of a 3-parameter probability density function (PDF), known as Burr distribution, to estimate the delay of each gate on the critical path. In this work, it is demonstrated that our proposed method is more accurate than previously proposed methods by taking into account the skewness of delay PDF. Although our proposed method is based on a 3-parameter PDF, we demonstrate that the simulation cost of our proposed method is no more than the conventional 2-parameter Gaussian PDF. We have compared the accuracy of our proposed method against the HSPICE simulation results. Moreover, we have compared the accuracy of our method with the most recent works with a 2-parameter PDF. The results for ISCAS85 benchmark circuits in our work have shown for 99 percentile points with average errors of 3.62, 3.49 and 2.78% in 90 nm, 45 nm and 22 nm technologies respectively.